An integrated circuit is a collection of electronic components (e.g., transistors) fabricated within a semiconductor device or chip. A single integrated circuit can contain millions of electronic components. Conductive lines connect the electronic components within the semiconductor devices to one another. These conductive lines are often referred to as “interconnect lines” or the “interconnect.” By connecting the electronic components to one another in a specific manner via the interconnect, the semiconductor devices can send signals to one another, thereby allowing the integrated circuit to perform different functions. For example, some integrated circuits can be designed to function as microprocessors and other integrated circuits can be designed to operate as memory.
Integrated circuits are designed using software design tools. It is very important that the design tools accurately model the physical characteristics of the electronic components and the interconnect. Accurate physical modeling using the software design tools increases the chances that a particular design will work properly the first time it is fabricated. Likewise, if a particular design is not modeled correctly, it is very likely that the design will not function properly when fabricated. In this situation, an integrated circuit designer must then attempt to determine why the design failed, make changes to the design, and fabricate another chip using the modified design. This iterative process significantly delays the time it takes to get the semiconductor product to market, causing companies to lose money and market share. In addition, the need to refabricate integrated circuit chips can lead to dramatically increased costs since the actual fabrication process is very expensive. It is therefore essential that the electronic components and the interconnects that connect these components are modeled accurately during the design phase of the integrated circuit chip.
To create accurate models of integrated circuit interconnects, integrated circuit designers must analyze fabricated semiconductor wafers to determine physical (actual) interconnect process parameters. Important process parameters include line width, metal thickness, and dielectric thickness. There are several known techniques that can be used to measure the actual interconnect process parameters. One commonly used measurement technique uses a destructive methodology, where a focused ion beam (“FIB”) cuts into a fabricated wafer exposing the cross section of an interconnect line and then a Scanning Electron Microscope (“SEM”) takes pictures of the exposed interconnect line. Unfortunately, this technique destroys the wafer. It also takes a relatively long period of time to make the measurements since the wafer must be cut and then analyzed using a microscope.
Non-destructive techniques can also be used to measure physical interconnect process parameters. One non-destructive technique uses optical metrology tools. Wafers are not damaged using this technique. The optical metrology tools make measurements quickly and the results can be easily interpreted. However, the resolution of current generation optical metrology tools limits their applications to sub-micron range (i.e., less than 100 nm).
In recent years, aggressive scaling of semiconductor process technologies has resulted in interconnect delays that have become larger than transistor gate delays. To address this problem, the semiconductor industry has began using copper as the interconnect material, rather than aluminum. This is because the signal delay through a copper interconnect is less than the signal delay through a aluminum interconnect. Due to low resistivity of copper, which is almost half of that of Aluminum, both the resistance and capacitance of the interconnect are reduced, resulting in a lower interconnect delay.
A disadvantage to using copper interconnects compared to aluminum interconnects is that it is more difficult to measure the process parameters of copper interconnects. It is well known that aluminum interconnect lines have a rectangular shape after processing, while copper interconnect lines have a trapezoidal shape after processing. However, most conventional measurement techniques are only capable of measuring the process parameters for interconnect lines having rectangular shapes. In fact, the only known technique for accurately measuring copper interconnect process parameters is the destructive SEM technique described above. As discussed above, obtaining measurements using the destructive SEM technique is time consuming, and results in the destruction of wafers. Non-destructive optical and e-beam tools cannot give information on both width (top and bottom) and thickness of the copper interconnects, because these techniques are only capable of measuring top view of the interconnects. It is essential to capture all three dimensions associated with copper interconnects for process control, parasitic extraction, circuit delay simulation, and parametric yield prediction.
Thus, given advances in semiconductor fabrication technologies, and in particular, the use of copper interconnects, there is a need for non-destructive techniques to determine the process parameters for interconnects having non-ideal (i.e., non-rectangular) shapes.